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fujitsu semiconductor data sheet copyright?2010-2011 fujitsu semicond uctor limited all rights reserved 2011.6 memory fram 128 k (16 k 8) bit i 2 c MB85RC128 description the MB85RC128 is a fram (ferroelectric random access memory) stand-alone chip in a configuration of 16,384 words 8 bits, using the ferroelectric process and silicon gate cmos process technologies for forming the nonvolatile memory cells. the MB85RC128 adopts the two-wire serial interface. unlike sram, the MB85RC128 is able to reta in data without using a data backup battery. the read/write endurance of the nonvolatile memory cells used for the MB85RC128 has improved to be at least 10 10 cycles, significantly out performing flash memory and e 2 prom in the number. the MB85RC128 does not need a polling sequence after writ ing to the memory such as the case of flash memory nor e 2 prom. features ? bit configuration : 16,384 words 8 bits ? operating power supply voltage : 2.7 v to 3.6 v ? operating frequency : 400 khz (max) ? two-wire serial interface : i 2 c-bus specification ver. 2.1 compliant, supports standard-mode/ fast-mode. fully controllable by two ports: serial clock (scl) and serial data (sda). ? operating temperature range : ? 40 c to +85 c ? data retention : 10 years ( + 75 c) ? read/write endurance : 10 10 times ? package : plastic / sop, 8-pin (fpt-8p-m02) ? low power consumption : operating current 0. 15 ma (max: @400 khz), standby current 5 a (typ) ds05?13110?3e www..net
MB85RC128 2 ds05?13110?3e pin assignment pin functional descriptions pin number pin name functional description 1 to 3 a0 to a2 device address pins the MB85RC128 can be connected to the same data bus up to 8 devices. device addresses are used in order to identify each of the devices. connect these pins to vdd pin or vss pin externally. only if the combination of vdd and vss pins matches a device, an address and a code inputted from the sda pin, the device operates. in the open pin state, a0, a1, and a2 pins are pulled-down and recognized as ?l?. 4 vss ground pin 5sda serial data i/o pin this is an i/o pin of serial data for performing bidirectional communication of address and writing or reading data of fr am memory cell array. it is an open drain output that may be wired or with other open drain or open collector sig- nals on the bus, so a pull-up resistance is required to be connected to the ex- ternal circuit. 6scl serial clock pin this is a clock input pin for input/output serial data. data is sampled on the ris- ing edge of the clock and output on the falling edge. 7wp write protect pin when write protect pin is ?h?, writing operation is disabled. when write protect pin is ?l?, the entire memory region can be overwritten. reading operation is al- ways enabled regardless of the write protect pin input level. the write protect pin is pulled down internally to vss pin, therefore if the write protect pin is open, the pin status is detected as ?l? (write enabled). 8 vdd supply voltage pin v ss sda a1 v dd scl a2 a0 w p 8 7 6 5 4 3 2 1 (top view) (fpt-8p-m02)
MB85RC128 ds05?13110?3e 3 block diagram i 2 c (inter-integrated circuit) the MB85RC128 has a two-wire serial interface, supports the i 2 c bus, and operates as a slave device. the i 2 c bus defines communication roles of ?master? and ?s lave? devices, with the master side holding the authority to initiate control. furthermore, a i 2 c bus connection is possible where a single master device is connected to multiple slave devices. in this case, it is necessary to assign a uni que device address to the slave device, the master side starts communication after specifying th e slave to communicate by addresses. ? i 2 c interface system configuration example w p a0, a1, a2 sda scl row decoder address counter fram array 16,384 8 serial/parallel converter column decoder/sense amp/ write amp control logic scl sda a2 a1 a0 000 a2 a1 a0 001 a2 a1 a0 010 ... i 2 c bus master i 2 c bus MB85RC128 i 2 c bus MB85RC128 i 2 c bus MB85RC128 pull-up resistors device address vdd
MB85RC128 4 ds05?13110?3e i 2 c communication protocol the i 2 c bus is a two wire serial interface that uses a bi directional data bus (sda) and serial clock (scl). a data transfer can only be initiated by the bus master, wh ich will also provide the serial clock for synchroni- zation. the sda signal should change while scl is lo w. however, as an exception, when starting and stopping communication sequence, sda is allowed to change while scl is high. ? start condition to start read or write operations by the i 2 c bus, change the sda input from high to low while the scl input is in the high state. ? stop condition to stop the i 2 c bus communication, change the sda input from low to high while the scl input is in the high state. in the reading operation, inputting the st op condition finishes reading and enters the standby state. in the writing operation, inputting the stop condition finishes inputting the rewrite data. ? start condition, stop condition note : the fram device does not need the programming wait time (t wc ) after issuing the stop condition during the write operation. scl sda start stop
MB85RC128 ds05?13110?3e 5 acknowledge (ack) in the i 2 c bus, serial data including address or memory inform ation is sent in units of 8 bits. the acknowledge signal indicates that every each 8 bits of the data is successfully sent and receiv ed. the information receiver side usually outputs ?l? every time on the 9th scl clock after each 8 bits are successfully transmitted. on the transmitter side, the bus is temporarily released to hi-z every time on this 9th clock to allow the acknowl- edge signal to be received and checked. during this hi-z-released period, the receiver side pulls the sda line down to indicate ?l? that the previous 8bits communication is successfully received. if the information receiver side det ects stop condition before driving th e acknowledge ?l?, the read operation ends and the i 2 c bus enters the standby state. if stop conditi on is not sent, nor does the transmitter detect the acknowledge ?l?, the bus remains in the released state ?h? without doing anything. ? acknowledge timing overview diagram scl 123 8 9 sda start ack the transmitter side should always release sda on the 9th bit. at this time, the rece iver side outputs a pull-down to indicate a successful byte transfer (ack response).
MB85RC128 6 ds05?13110?3e device address word (slave address) following the start condition, the bus master sends the 8bits device address word (slave address) to start i 2 c communication. the device address word (8bits) consis ts of a device type code (4bits), device address code (3bits), and a read/write code (1bit). ? device type code (4bits) the upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at ?1010? for the MB85RC128. ? device address code (3bits) following the device type code, the 3 bits of the devi ce address code are input in order of a2, a1, and a0 pins. each MB85RC128 is given a unique 3bits code on the device address pin (external hardware pin a2, a1, and a0). when the device address code is received by the slave device, the slave only responds if the hardware device address of which is equal to its unique 3bits code. ? read/write code (1bit) the 8th bit of the device address word is the r/w (read/write) code. when the r/w code is ?l?, a write operation is enabled, and the r/w code is ?h?, a read operation is enabled for the MB85RC128.
MB85RC128 ds05?13110?3e 7 data structure in the i 2 c bus, the acknowledge ?l? is output on the 9th bit after the 8 bits of the device and address word following the start condition. after confirming the acknowledge response at the slave, the i 2 c master outputs 8bits 2 memory address to the i 2 c slave. when the memory address input ends, the slave again outputs the acknowledge ?l?. after this operation, the i/o data follows in units of 8 bits, with the acknowledge ?l? output after every 8bits. it is determined by the r/w code whether the data li ne is driven by the master or the slave. for a write operation the slave will accept 8bits from the master then send an acknowledge. if the master detects the acknowledge, the master will transfer the next 8bits. for a read operation the slave will place 8bits on the i 2 c bus, then wait for an acknowledge from the master. ? data structure diagram fram acknowledge -- polling not required the MB85RC128 performs write operations at the same speed as read operations, so any waiting time for an ack polling* does not occur. the wr ite cycle takes no additional time. *: as to e 2 prom, the acknowledge polling is performed as a progress check in the write programming step. it places nak condition on the bus as of ?not ackn owledged? during the writing programming period. the busy status for the write programming is given from 9th ack bit. that ?done? condition is placed onto i 2 c bus by e 2 prom i 2 c device and your program had to poll the bus in order to sense that condition. write protect (wp) the entire memory array can be write protected using t he write protect pin. when the write protect is set to ?h?, the entire memory map will be write protected. when the write protect pin is ?l?, all addresses may be overwritten. note : the write protect pin is pulled down internally to vss pin, therefore if the write protect pin is open, the pin status is detected as low (write enabled). .. .. start ack 1234567 8 91 2 scl sda ack start condition a s s 10 10 a2 a1 a0 r/ w a access from master access from slave
MB85RC128 8 ds05?13110?3e command ? byte write if the 8th bit of the device address word (r/w = 0) is sent following the start condition, the slave responds with an ack. after this ack, writ e addresses and data are sent in the same way, and the write ends by master, generating a stop condition at the end. note : in the MB85RC128, input ?00? as the upper 2 bits of the msb. ? page write if additional 8bits are sent after the same command as byte write, a page write is performed. if more bytes are sent than will fit up to the end of t he address, the address rolls over to 0000 h . therefore, if more than 8kbytes are sent, the data is overwritten in order star ting from the start of the fram memory address that was written first. because fram performs write opera tions at bus speed, the data will be written to fram after the ack response finishes immediately. note : it is not necessary to take a period for internal write programming cycles from the buffer to the memory after the stop condition is generated. lsb start condition stop condition ack a s p msb 00xxxxxx xxxxxxxx s a2 a1 a0 a a a a p address high 8b its address lo w 8b its w rite data 8b its 0 1 010 access from master access from slave start condition stop condition ack a s p s a2 a1 a0 a a a a a p address high 8b its address lo w 8b its w rite data 8b its w rite data ... 0 1 010 access from master access from slave
MB85RC128 ds05?13110?3e 9 ? current address read when the previous write or read operation finishes su ccessfully up to the stop command and if the last accessed address is taken to be ?n ?, then the address at ?n+1? is r ead by sending the following command unless turning the power off. if the end of the address range is reached internally, the address counter will roll over to 0000 h . the current address is undefined imm ediately after the power is turned on. ? random read the one byte of data at the address as saved in the bu ffer can be read out synchronously to scl by specifying the address in the same way as for a write, and then is suing another start condition and sending the control byte (r/w = 1). the final nack is issued by the receiver that receives the data. in this case, this bit is issued by the master side. start condition stop condition ack a s p n ack n s a2 a1 a0 a n p read data 8b its (n+1) address 1 1 010 access from master access from slave start condition stop condition ack a s p n ack n s a2 a1 a0 a a a p address high 8b its address lo w 8b its n address 0 1 010 s a2 a1 a0 a 1 1 010 read data 8b its n access from master access from slave
MB85RC128 10 ds05?13110?3e ? sequential read data can be received continuously following the control byte after specifying the address the same as for random read. if the read exceed s the end of address for the MB85RC128, the internal read address automatically rolls over to 0000 h . stop condition ack a p n ack n aa a n p read data 8b its read data 8b its read data ... ... access from master access from slave
MB85RC128 ds05?13110?3e 11 absolute maximum ratings * : these parameters are based on the condition that vss is 0 v. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. recommended operating conditions * : these parameters are based on the condition that vss is 0 v. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application out side the listed conditions are advised to contact their representatives beforehand. parameter symbol rating unit min max power supply voltage* v cc ? 0.5 +4.0 v input pin voltage* v in ? 0.5 v cc + 0.5 ( 4.0) v output pin voltage* v out ? 0.5 v cc + 0.5 ( 4.0) v ambient temperature t a ? 40 + 85 c storage temperature tstg ? 40 + 125 c parameter symbol value unit min typ max power supply voltage* v cc 2.7 3.3 3.6 v ?h? level input voltage* v ih v cc 0.8 ? v cc + 0.5 ( 4.0) v ?l? level input voltage* v il ? 0.5 ? + 0.6 v ambient temperature t a ? 40 ? + 85 c
MB85RC128 12 ds05?13110?3e electrical characteristics 1. dc characteristics (within recommended operating conditions) 2. ac characteristics ac characteristics were measured under the following measurement conditions. power supply voltage : 2.7 v to 3.6 v operating temperature : ? 40 c to + 85 c input voltage magnitude : 0.3 v to 2.7 v input rise time : 5 ns input fall time : 5 ns input judge level : v cc /2 output judge level : v cc /2 parameter symbol condition value unit min typ max input leakage current |i li | scl, sda = 0 v to v cc a0, a1, a2, wp = 0 v or v cc ?? 1 a output leakage current |i lo |v out = 0 v to v dd ?? 1 a operating power supply current i cc scl = 400 khz ? 100 150 a standby current i sb scl, sda = v cc a0, a1, a2, wp = 0 v or v cc ? 520 a ?l? level output voltage v ol i ol = 2 ma ?? 0.4 v parameter symbol value unit min max scl clock frequency fscl 0 400 khz clock high time t high 600 ? ns clock low time t low 1300 ? ns scl/sda rise time t r ? 300 ns scl/sda fall time t f ? 300 ns start condition hold t hd:sta 600 ? ns start condition setup t su:sta 600 ? ns sda input hold t hd:dat 0 ? ns sda input setup t su:dat 100 ? ns sda output hold t dh:dat 0 ? ns stop condition setup t su:sto 600 ? ns sda output access after scl fall t aa ? 900 ns pre-charge time t buf 1300 ? ns pulse width ignored (input filter on scl and sda) t sp ? 50 ns
MB85RC128 ds05?13110?3e 13 3. ac timing definitions 4. pin capacitance parameter symbol conditions value unit min typ max i/o capacitance c i/o v in = v out = 0 v, f = 1 mhz, t a = + 25 c ?? 15 pf input capacitance c in ?? 15 pf start start stop stop v alid scl sda scl sda scl sda v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v ih v ih t su:dat t su:sta t hd:sta t high t lo w t dh:dat 1/fscl t su:sto t hd:dat v ih v ih v ih v il v il v il v il v il v il v il v il t bu f t f t r t f t r t aa t sp
MB85RC128 14 ds05?13110?3e 5. ac test load circuit 3.3 v 1 k 100 pf o u tp u t
MB85RC128 ds05?13110?3e 15 power on sequence notes on use ? data written before performing ir reflow is not guaranteed. ? vdd pin is required to be rising from 0 v because tu rning the power on from an intermediate level may cause malfunctions, when the power is turned on. during the access period from the start condition to the stop condition, keep the level of wp, a0, a1, and a2 pins to ?h? or ?l?. parameter symbol value unit min max sda, scl level hold time during power down tpd 85 ? ns sda, scl level hold time during power up tpu 85 ? ns power supply rise time tr 10 ? s 0 v sda, scl > v cc 0. 8 * sda, scl > v cc 0. 8 * tpd tp u tr v il (max) 1.0 v v ih (min) 2.7 v v cc sda, scl : don ' t care sda, scl sda, scl 0 v v il (max) 1.0 v v ih (min) 2.7 v v cc * : sda, scl (max) < v cc + 0.5 v
MB85RC128 16 ds05?13110?3e ordering information part number package remarks MB85RC128pnf-g-jne1 8-pin, plastic sop (fpt-8p-m02) MB85RC128pnf-g-jnere1 8-pin, plastic sop (fpt-8p-m02) embossed carrier tape
MB85RC128 ds05?13110?3e 17 package dimension please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 8-pin plastic sop lead pitch 1.27 mm package width package length 3.9 mm 5.05 mm lead shape gullwing sealing method plastic mold mounting height 1.75 mm max weight 0.06 g 8-pin plastic sop (fpt-8p-m02) (fpt-8p-m02) c 2002-2010 fujitsu semiconductor limited f08004s-c-4-9 1.27(.050) 3.900.30 6.000.40 .199 ?.008 +.010 ?0.20 +0.25 5.05 0.13(.005) m (.154.012) (.236.016) 0.10(.004) 14 5 8 0.440.08 (.017.003) ?0.07 +0.03 0.22 .009 +.001 ?.003 45 0.40(.016) "a" 0~8 0.25(.010) (mounting height) details of "a" part 1.550.20 (.061.008) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.150.10 (.006.004) (stand off) 0.10(.004) * 1 * 2 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * 1 : these dimensions include resin protrusion. note 2) * 2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder.
MB85RC128 18 ds05?13110?3e memo
MB85RC128 ds05?13110?3e 19 memo
MB85RC128 fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 902 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/se rvices/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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